Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Improving cache lifetime reliability at ultra-low voltages
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Radiation-induced Soft Errors: A Chip-level Modeling Perspective
Foundations and Trends in Electronic Design Automation
Evaluating application vulnerability to soft errors in multi-level cache hierarchy
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing - Volume 2
An energy-efficient L2 cache architecture using way tag information under write-through policy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Soft error rates measured on embedded SRAMs in a 65nm CMOS technology show a significant increase of the error rate induced by neutron radiation (NSER), while the number of soft errors due to alpha radiation (ASER) is within the expected range. In this paper it will be discussed, that the increase of the NSER values is caused by an unexpected high number of single event upsets (SEU) that flip multiple SRAM cells simultaneously (multi-bit upset). As root cause radiation induced switching of parasitic bipolar transistors was found.