Quantitative system performance: computer system analysis using queueing network models
Quantitative system performance: computer system analysis using queueing network models
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Terrestrial cosmic ray intensities
IBM Journal of Research and Development
Fault Injection in VHDL Descriptions and Emulation
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Timing Models for MOS Circuits
Timing Models for MOS Circuits
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Cache Scrubbing in Microprocessors: Myth or Necessity?
PRDC '04 Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04)
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Computing Architectural Vulnerability Factors for Address-Based Structures
Proceedings of the 32nd annual international symposium on Computer Architecture
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient static algorithm for computing the soft error rates of combinational circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Soft Error Rates of Hardened Sequentials utilizing Local Redundancy
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Soft-error resilience of the IBM POWER6 processor
IBM Journal of Research and Development
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology
IBM Journal of Research and Development
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model
IEEE Transactions on Dependable and Secure Computing
Soft-Error-Rate-Analysis (SERA) Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit Reliability Analysis Using Symbolic Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantitative evaluation of soft error injection techniques for robust system design
Proceedings of the 50th Annual Design Automation Conference
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Chip-level soft-error rate (SER) estimation can come from two sources: direct experimental measurement and simulation. Because SER mitigation decisions need to be made very early in the product design cycle, long before product Si is available, a simulation-based methodology of chip-level radiation-induced soft error rates that is fast and reasonably accurate is crucial to the reliability and success of the final product. The following contribution summarizes selected publications that are deemed relevant by the author to enable a truly chip-level radiation-induced soft error rate estimation methodology. Although the strategies and concepts described have microprocessors manufactured in bulk CMOS technologies in mind, there is no fundamental reason why they cannot be applied to other technologies and different types of integrated circuits (ICs).