An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
Decomposing a permutation into a conjugated tensor product
ISSAC '97 Proceedings of the 1997 international symposium on Symbolic and algebraic computation
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Improving Gate-Level Simulation of Quantum Circuits
Quantum Information Processing
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Probabilistic maximum error modeling for unreliable logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Accurate and scalable reliability analysis of logic circuits
Proceedings of the conference on Design, automation and test in Europe
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tracking Uncertainty with Probabilistic Logic Circuit Testing
IEEE Design & Test
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A strategy for reliability assessment of future nano-circuits
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
VEBoC: variation and error-aware design for billions of devices on a chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Emerging nanodevice paradigm: Graphene-based electronics for nanoscale computing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Organizing wires for reliability in magnetic QCA
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Error immune logic for low-power probabilistic computing
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A general mathematical model of probabilistic ripple-carry adders
Proceedings of the Conference on Design, Automation and Test in Europe
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Radiation-induced Soft Errors: A Chip-level Modeling Perspective
Foundations and Trends in Electronic Design Automation
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic error modeling for nano-domain logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On pedagogy of nanometric circuit reliability
The Journal of Supercomputing
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
Journal of Electronic Testing: Theory and Applications
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design
Proceedings of the Conference on Design, Automation and Test in Europe
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
RAG: an efficient reliability analysis of logic circuits on graphics processing units
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence of soft errors, which involves combining the PTMs of gates to form an overall circuit PTM. Information such as output probabilities, the overall probability of error, and signal observability can then be extracted from the circuit PTM. We employ algebraic decision diagrams (ADDs) to improve the efficiency of PTM operations. A particularly challenging technical problem, solved in our work, is to simultaneously extend tensor products and matrix multiplication in terms of ADDs to non-square matrices. Our PTM-based method enables accurate evaluation of reliability for moderately large circuits and can be extended by circuit partitioning. To demonstrate the power of the PTM approach, we apply it to several problems in fault-tolerant design and reliability improvement.