Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy Aware Computing through Probabilistic Switching: A Study of Limits
IEEE Transactions on Computers
Probabilistic arithmetic and energy efficient embedded signal processing
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A More Precise Model of Noise Based PCMOS Errors
DELTA '10 Proceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
Modeling of Probabilistic Ripple-Carry Adders
DELTA '10 Proceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
Digital Integrated Circuits
Models for characterizing noise based PCMOS circuits
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible to trade correctness of circuit operations for potentially significant energy saving. For systematic design of probabilistic circuits, accurate mathematical models are indispensable. To this end, we propose a model of probabilistic ripple-carry adders. Compared to existing models, ours is applicable under a wide range of noise assumptions, including the popular additive-noise assumption. Our model provides recursive equations that can accurately capture propagation of carry errors. The proposed model is validated by HSPICE simulation, and we find that the model is able to predict multi-bit error-rates of a simulated probabilistic ripple-carry adder with reasonable accuracy.