A general mathematical model of probabilistic ripple-carry adders
Proceedings of the Conference on Design, Automation and Test in Europe
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Models for characterizing noise based PCMOS circuits
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Hi-index | 0.00 |
In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization proposed here can enable accurate multi-bit models based on fast mathematical extrapolation instead of expensive and slow HSPICE simulations.