Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Limits to Voltage Scaling from the Low Power Perspective
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Arithmetic and Logic in Computer Systems
Arithmetic and Logic in Computer Systems
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Energy Aware Computing through Probabilistic Switching: A Study of Limits
IEEE Transactions on Computers
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Probabilistic system-on-a-chip architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Energy-aware probabilistic multiplier: design and analysis
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Error immune logic for low-power probabilistic computing
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A general mathematical model of probabilistic ripple-carry adders
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing energy to minimize errors in dataflow graphs using approximate adders
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A probabilistic Boolean logic for energy efficient circuit and system design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic knobs for responsive power-aware computing
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
An approach to energy-error tradeoffs in approximate ripple carry adders
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Proceedings of the 9th conference on Computing Frontiers
Accuracy-configurable adder for approximate arithmetic designs
Proceedings of the 49th Annual Design Automation Conference
Ten Years of Building Broken Chips: The Physics and Engineering of Inexact Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
Models for characterizing noise based PCMOS circuits
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Probabilistic arithmetic, where the ith output bit of addition and multiplication is correct with a probability pi , is shown to be a vehicle for realizing extremely energy-efficient, embedded computing. Specifically, probabilistic adders and multipliers, realized using elements such as gates that are in turn probabilistic, are shown to form a natural basis for primitives in the signal processing (DSP) domain. In this paper, we show that probabilistic arithmetic can be used to compute the FFT in an extremely energy-efficient manner, yielding energy savings of over 5. 6X in the context of the widely used synthetic aperture radar (SAR) application [1]. Our results are derived using novel probabilistic cmos (PC-MOS) technology, characterized and applied in the past to realize ultra-efficient architectures for probabilistic applications [2, 3, 4]. When applied to the dsp domain, the resulting error in the output of a probabilistic arithmetic primitive, such as an adder for example, manifests as degradation in the signal-to-noise ratio (SNR) ofthe sar image that is reconstructed through the FFT algorithm. In return for this degradation that is enabled by our probabilistic arithmetic primitives ?- degradation visually indistinguishable from an image reconstructed using conventional deterministic approaches -- significant energy savings and performance gains are shown to be possible per unit of SNR degradation. These savings stem from a novel method of voltage scaling, which we refer to as biased voltage scaling (or BIVOS), that is the major technical innovation on which our probabilistic designs are based.