An approach to energy-error tradeoffs in approximate ripple carry adders

Authors:
Zvi M. Kedem;Vincent J. Mooney;Kirthi Krishna Muntimadugu;Krishna V. Palem
Affiliations:
New York University, New York, NY, USA;Nanyang Technological University, Singapore, Singapore;Rice University, Houston, TX, USA;Rice University, Houston, TX, USA
Venue:
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Year:
2011

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Abstract

Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58X and by a median of 1.58X in 90nm transistor technology.