A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management

  • Authors:

  • Tatsuya Kamei;Tetsuhiro Yamada;Takao Koike;Masayuki Ito;Takahiro Irita;Kenichi Nitta;Toshihiro Hattori;Shinichi Yoshioka

  • Affiliations:

  • Renesas Technology Corp., Tokyo, Japan;Renesas Technology Corp., Tokyo, Japan;Renesas Technology Corp., Tokyo, Japan;Renesas Technology Corp., Tokyo, Japan;Renesas Technology Corp., Tokyo, Japan;Renesas Technology Corp., Tokyo, Japan;Renesas Technology Corp., Tokyo, Japan;Renesas Technology Corp., Tokyo, Japan

  • Venue:
  • Proceedings of the 2009 Asia and South Pacific Design Automation Conference
  • Year:
  • 2009

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Abstract

A Dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the Partial Clock Activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory footprint by 43MB, sharing external memory among CPUs and HW-IPs using virtual address space that enables reuse of physically fragmented memory.