The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Counterflow Pipeline Processor Architecture
Counterflow Pipeline Processor Architecture
Circuit-aware architectural simulation
Proceedings of the 41st annual Design Automation Conference
Reducing pipeline energy demands with local DVS and dynamic retiming
Proceedings of the 2004 international symposium on Low power electronics and design
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Proceedings of the 43rd annual Design Automation Conference
Energy management for real-time embedded systems with reliability requirements
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Robust estimation of parametric yield under limited descriptions of uncertainty
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
Working with process variation aware caches
Proceedings of the conference on Design, automation and test in Europe
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Variable latency caches for nanoscale processor
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems
Proceedings of the 45th annual Design Automation Conference
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
Proceedings of the 45th annual Design Automation Conference
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Enhanced reliability-aware power management through shared recovery technique
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms
Journal of Electronic Testing: Theory and Applications
Multicore soft error rate stabilization using adaptive dual modular redundancy
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable stochastic processors
Proceedings of the Conference on Design, Automation and Test in Europe
Reliability-aware dynamic energy management in dependable embedded real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
Low-power multimedia system design by aggressive voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring the fidelity-efficiency design space using imprecise arithmetic
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An approach to energy-error tradeoffs in approximate ripple carry adders
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Significance driven computation on next-generation unreliable platforms
Proceedings of the 48th Design Automation Conference
Generalized reliability-oriented energy management for real-time embedded applications
Proceedings of the 48th Design Automation Conference
Reliable software for unreliable hardware: embedded code generation aiming at reliability
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A self-checking hardware journal for a fault-tolerant processor architecture
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Active management of timing guardband to save energy in POWER7
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Maestro: orchestrating lifetime reliability in chip multiprocessors
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems
Journal of Systems and Software
Instruction scheduling for reliability-aware compilation
Proceedings of the 49th Annual Design Automation Conference
Resilient and adaptive performance logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Low-power adaptive RF system design using real-time fuzzy noise-distortion control
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
Proceedings of the 39th Annual International Symposium on Computer Architecture
Nanoscale technologies: prospect or hazard to dependable and secure computing?
LADC'07 Proceedings of the Third Latin-American conference on Dependable Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 7th International Conference on Body Area Networks
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
Reliability challenges of real-time systems in forthcoming technology nodes
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive reduction of the frequency search space for multi-vdd digital circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting program-level masking and error propagation for constrained reliability optimization
Proceedings of the 50th Annual Design Automation Conference
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
Variation-aware voltage level selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems and Software
Performance boosting under reliability and power constraints
Proceedings of the International Conference on Computer-Aided Design
Inexact computing using probabilistic circuits: Ultra low-power digital processing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Dynamic voltage scaling is one of the more effective and widely used methods for power-aware computing. Here is a dvs approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins.