Vector quantization and signal compression
Vector quantization and signal compression
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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
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Proceedings of the 41st annual Design Automation Conference
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VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Considering process variations during system-level power analysis
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ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Temperature-aware voltage selection for energy optimization
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Variation-aware system-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we address the problem of variation-aware selection of voltage levels for system-on-chips (SoCs) that are organized into multiple frequency and voltage domains. Conventionally, the voltage levels for each domain, as well as the mapping between frequencies and voltages, are determined without considering variations. In the presence of variations, these choices are often suboptimal since the frequency versus voltage characteristics vary from one SoC instance to another and across different voltage domains within an instance. We present a two-pronged approach to address this problem. First, we propose breaking the conventional fixed coupling between voltage levels and frequencies and demonstrate that performing this association based on the characteristics of individual chip instances can lead to significant improvements in power and performance. Second, we show that voltage levels that are computed while accounting for variations can lead to further improvements. We present a methodology to determine a set of discrete voltage levels in a variation-aware manner by generating and quantizing the ideal voltage distribution for a given SoC. Our experiments on an 802.11 MAC processor SoC indicate that the proposed techniques lead to significant improvements in power and performance characteristics in the presence of variations. We obtained an improvement of up to 68% in parametric yield (number of chips meeting power and performance targets) compared to conventional voltage scaling.