Evaluation of voltage interpolation to address process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating design of voltage interpolation to address process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Variation-aware voltage level selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
Increasing levels of process variation in current process technologies make it extremely important that design and process decisions be made while considering their impact. This paper presents a convex-optimization-based approach to select values of supply voltages, threshold voltages, and oxide thicknesses to minimize power dissipation in a simplified abstraction of multi-Vdd/Vth/Tox CMOS designs while considering process variation. The authors use this probabilistic approach to perform optimization of different statistical parameters of power dissipation (e.g., mean or high percentile points) and quantify the impact of rising process variations on these power-minimization techniques