An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Low-power design methodology and applications utilizing dual supply voltages
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Local Search in Combinatorial Optimization
Local Search in Combinatorial Optimization
High Level Synthesis for Peak Power Minimization Using ILP
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing total power by simultaneous Vdd/Vth assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3DHLS: incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
The ever-increasing chip power dissipation in SoCs has imposed great challenges on today's circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vdd optimizations are performed under deterministic conditions. With the increasing process variability that has significant impact on both the power dissipation and performance of circuit designs, it is necessary to employ statistical approaches in analysis and optimizations for low power. This paper studies the impact of process variations on the multi-Vth/Vdd technique at the behavioral synthesis level. A multi-Vth/Vdd resource library is characterized for delay and power variations at different voltage combinations. A parametric yield-driven resource binding algorithm is then proposed, which uses the characterized power and delay distributions and efficiently maximizes power yield under a timing yield constraint. During the resource binding process, voltage level converters are inserted between resources when required. Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worst-case based deterministic approaches.