Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Level conversion for dual-supply systems
Proceedings of the 2003 international symposium on Low power electronics and design
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Robust level converter design for sub-threshold logic
Proceedings of the 2006 international symposium on Low power electronics and design
Digital Circuit Optimization via Geometric Programming
Operations Research
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single stage static level shifter design for subthreshold to I/O voltage conversion
Proceedings of the 13th international symposium on Low power electronics and design
A new family of sequential elements with built-in soft error tolerance for dual-VDD systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Compiler-assisted soft error detection under performance and energy constraints in embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing branch misprediction penalties via adaptive pipeline scaling
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Logical effort based dynamic power estimation and optimization of static CMOS circuits
Integration, the VLSI Journal
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Low-power subthreshold to above threshold level shifters in 90nm and 65nm process
Microprocessors & Microsystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power and high speed multi threshold voltage interface circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power dual-edge triggered state retention scan flip-flop
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
High-performance low-energy STT MRAM based on balanced write scheme
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
STT-RAM designs supporting dual-port accesses
Proceedings of the Conference on Design, Automation and Test in Europe
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Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Additionally, circuit robustness against supply bounce is a key property that differentiates good level converter design. Novel flip-flops presented in this paper incorporate a half-latch level converter and a precharged level converter. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip-flop. These benefits are accompanied by 24% flip-flop robustness improvement leading to 13% delay spread reduction in a CVS critical path. The proposed flip-flops also show 18% layout area reduction. Advantages of level conversion in a flip-flop over asynchronous level conversion in combinational logic are also discussed in terms of delay penalty and its sensitivity to supply bounce.