Reducing branch misprediction penalties via adaptive pipeline scaling

Authors:
Chang-Ching Yeh;Kuei-Chung Chang;Tien-Fu Chen;Chingwei Yeh
Affiliations:
National Chung Cheng University, Chia-Yi, Taiwan, R.O.C.;National Chung Cheng University, Chia-Yi, Taiwan, R.O.C.;National Chung Cheng University, Chia-Yi, Taiwan, R.O.C.;National Chung Cheng University, Chia-Yi, Taiwan, R.O.C.
Venue:
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Year:
2007

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Abstract

Pipeline scaling provides an attractive solution for increasingly serious branch misprediction penalties within deep pipeline processor. In this paper we investigate Adaptive Pipeline Scaling (APS) techniques that are related to reducing branch misprediction penalties. We present a dual supply-voltage architecture framework that can be efficiently exploited in an deep pipeline processor to reduce pipeline depth depending on the confidence level of branches in pipeline. We also propose two techniques, Dual Path Index Table (DPIT) and Step-By-Step (STEP) manner, that increase the efficiency for pipeline scaling. With these techniques, we then show that APS not only provides a fast branch misprediction recovery, but also speeds up the resolve of mispredicted branch. The evaluation of APS in a 13-stage superscalar processor with benchmarks from SPEC2000 applications shows a performance improvement (between 3%-12%, average 8%) over baseline processor that does not exploit APS.