Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low Power Adder with Adaptive Supply Voltage
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Reducing branch misprediction penalties via adaptive pipeline scaling
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Optimized design of parallel carry-select adders
Integration, the VLSI Journal
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Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. A proposed level converter based on the Complementary Pass Transistor Logic (CPL) cancels out the delay penalty of level conversion. We achieved 26% power improvement on a 128-bit CSA prototype over a conventional design with same performance.