Low-power carry-select adder using adaptive supply voltage based on input vector patterns
Proceedings of the 2004 international symposium on Low power electronics and design
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
Error Analysis for the Support of Robust Voltage Scaling
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variable-latency adder (VL-adder) designs for low power and NBTI tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Demands for the low power VLSI have been pushing thedevelopment of aggressive design methodologies to reducethe power consumption drastically. To meet the growingdemand, we propose a low power adder, which adaptivelyselects supply voltages based on the input vector patterns.We prototyped a 32-bit Ripple Carry Adder and analyzedthe power consumption and performance in details.Results show 29% improvement in power consumptionover a conventional ripple carry adder with comparableperformance.