Communications of the ACM
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
Deep-Submicron Microprocessor Design Issues
IEEE Micro
Analysis of a Control Mechanism for a Variable Speed Processor
IEEE Transactions on Computers
The SNAP Project: Design of Floating Point Arithmetic Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Optimal design of synchronous circuits using software pipelining techniques
ICCD '98 Proceedings of the International Conference on Computer Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
The Design of an Asynchronous Microprocessor
The Design of an Asynchronous Microprocessor
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Low Power Adder with Adaptive Supply Voltage
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Data Dependence of Delay Distribution for a Planar Bus
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
VariPipe: low-overhead variable-clock synchronous pipelines
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Variable-latency design by function speculation
Proceedings of the Conference on Design, Automation and Test in Europe
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Proceedings of the Conference on Design, Automation and Test in Europe
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 14.98 |
Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock frequency and, hence, performance. However, much more performance can be obtained under typical operating conditions through experimentation, but such increased frequency operation is subject to the possibility of system failure and, hence, data loss/corruption. Further, mobile CPUs such as those in cell phones/internet browsers do not adapt to their current surroundings (varying temperature conditions, etc.) so as to increase or decrease operating frequency to maximize performance and/or allow operation under extreme conditions. We present a digital hardware design technique realizing adaptive clock-frequency performance-enhancing digital hardware; the technique can be tuned to approximate performance maximization. The cost is low and the design is straightforward. Experiments are presented evaluating such a design in a pipelined uniprocessor realized in a Field Programmable Gate Array (FPGA).