Interconnect modeling and optimization in deep sub-micron technologies
Interconnect modeling and optimization in deep sub-micron technologies
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
Statistical interconnect metrics for physical-design optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to coupling between lines, the delay in a bus depends on the type of transition causing the delay. For a given sequence of data there is a delay distribution that depends on the sequence characteristics (correlation between consecutive data). This information opens the possibility to reduce the clock cycle for a system with error correcting schemes that handles the slower cases. The large number of transitions needed to calculate a realistic bus delay distribution make the use of electrical simulation impractical for obtaining the delay distribution. This paper presents calculations of the delay distribution for representative cases of sequences, using a computationally efficient method based on a reduced number of electrical simulations. It is shown that for quasi consecutive sequences, the most probable delay is considerably lower than worst case delay.