Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Active management of timing guardband to save energy in POWER7
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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In the past few years, many techniques have been introduced which try to utilize excessive timing margins of a processor. However, these techniques have limitations due to one of the following reasons: first, they are not suitable for high-performance processor designs due to the power and design overhead they impose; second, they are not accurate enough to effectively exploit the timing margins, requiring substantial safety margin to guarantee correct operation of the processor. In this paper, we introduce an alternative, more effective technique that is suitable for high-performance processor designs, in which a processor predicts timing errors in the critical paths and undertakes preventive steps in order to avoid the errors in the event that the timing margins fall below a critical level. This technique allows a processor to exploit timing margins, while only requiring the minimum safety margin. Our simulation results show that proposed idea results in 12% and 6% improvement in energy and Energy-Delay Product (EDP), respectively, over a Razor-based speculative method.