The SNAP Project: Design of Floating Point Arithmetic Units

Authors:
Stuart F. Oberman;Hesham Al-Twaijry;Michael J. Flynn
Affiliations:
-;-;-
Venue:
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Year:
1997

Citing 0
Cited 14

Leading-One Prediction with Concurrent Position Correction

IEEE Transactions on Computers
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm

IEEE Transactions on Computers
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication

IEEE Transactions on Computers - Special issue on computer arithmetic
A Low Power Approach to Floating Point Adder Design for DSP Applications

Journal of VLSI Signal Processing Systems
Multilevel Reverse-Carry Addition: Single and Dual Adders

Journal of VLSI Signal Processing Systems
AMD 3DNow! Technology: Architecture and Implementations

IEEE Micro
A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Montgomery's Multiplication Technique: How to Make It Smaller and Faster

CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Multilevel Reverse-Carry Adder

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Delay-Optimized Implementation of IEEE Floating-Point Addition

IEEE Transactions on Computers
Modified booth truncated multipliers

Proceedings of the 14th ACM Great Lakes symposium on VLSI
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control

IEEE Transactions on Computers
Lightweight floating-point arithmetic: case study of inverse discrete cosine transform

EURASIP Journal on Applied Signal Processing
Dual-mode floating-point adder architectures

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.01

Visualization

Abstract

The multiplier of a S/390 CMOS microprocessor is described. It is implemented in an aggressive static CMOS technology with 0.20 \mum effective channel length. The multiplier has been demonstrated in a single-image shared-memory multiprocessor at frequencies ...