Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
What every computer scientist should know about floating-point arithmetic
ACM Computing Surveys (CSUR)
Power comparisons for barrel shifters
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Design issues in high performance floating point arithmetic units
Design issues in high performance floating point arithmetic units
Leading-One Prediction with Concurrent Position Correction
IEEE Transactions on Computers
A Variable Latency Pipelined Floating-Point Adder
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
The SNAP Project: Design of Floating Point Arithmetic Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
A low power approach to floating point adder design
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
On low power floating point data path architectures
On low power floating point data path architectures
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection
Journal of Signal Processing Systems
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The demand for high performance, low power floating point adder cores has been on the rise during the recent years particularly for DSP applications. In this paper, we present a new architecture for a low power, IEEE compatible, floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, clock gated data paths allows activity reduction. The switching activity function of the proposed adder is represented as a three state FSM. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipatory logic as well as data path simplifications. In contrast to conventional high speed floating point adders that use leading zero anticipatory logic, the proposed scheme offers a worst case power reduction of 50%.