A Low Power Approach to Floating Point Adder Design for DSP Applications
Journal of VLSI Signal Processing Systems
Lightweight floating-point arithmetic: case study of inverse discrete cosine transform
EURASIP Journal on Applied Signal Processing
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
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We present a new architecture of a low power floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, controlled data paths allows activity reduction. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipation logic as well as data path simplifications. The proposed scheme offers a 10/spl times/ reduction in power consumption in comparison to that of conventional high speed floating point adders that use leading zero anticipation logic, for IEEE single precision floating point data format. The reduction in power delay product is about 16/spl times/. The corresponding figures for double precision units are around 40/spl times/ and 66/spl times/ respectively.