Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Journal of the ACM (JACM)
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
A low power approach to floating point adder design
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Modified Booth Modulo 2^n-1 Multipliers
IEEE Transactions on Computers
Computer Networks: A Systems Approach, 3rd Edition
Computer Networks: A Systems Approach, 3rd Edition
VLSI Implementation of new arithmetic residue to binary decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
| Hi-index | 14.98 |
Novel modulo 2n-1 addition algorithms for RNS applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures do not only offer significant speed-up in modulo 2n-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area x delay2 and energy x delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130nm CMOS technology.