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Error-control coding for computer systems
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Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Computer arithmetic algorithms
Computer arithmetic algorithms
A proposal for a new block encryption standard
EUROCRYPT '90 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
Data communications, computer networks and open systems (4th ed.)
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A Simplified Architecture for Modulo (2n + 1) Multiplication
IEEE Transactions on Computers
Journal of the ACM (JACM)
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection
IEICE - Transactions on Information and Systems
High-radix residue arithmetic bases for low-power DSP systems
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Improved area-efficient weighted modulo 2n+ 1 adder design with simple correction schemes
IEEE Transactions on Circuits and Systems II: Express Briefs
Residue arithmetic for designing low-power multiply-add units
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
On the design of modulo 2n+1 dot product and generalized multiply-add units
Computers and Electrical Engineering
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
Integration, the VLSI Journal
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In this paper, we present new design methods for modulo 2n卤 1 adders. We use the same select-prefix addition block for both modulo 2n - 1 and diminished-one modulo 2^n+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.