Regular, area-time efficient carry-lookahead adders
Journal of Parallel and Distributed Computing
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
Area-Time Optimal Adder Design
IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
Introduction to VLSI Systems
Structure of Computers and Computations
Structure of Computers and Computations
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
IEEE Transactions on Computers
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
A high-speed energy-efficient 64-bit reconfigurable binary adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
Modified Booth Modulo 2^n-1 Multipliers
IEEE Transactions on Computers
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Constant addition with flagged binary adder architectures
Integration, the VLSI Journal
Conventional adders with fine grained redundancy injection
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICECS'05 Proceedings of the 4th WSEAS international conference on Electronics, control and signal processing
Efficient modulo 2n±1 squarers
Integration, the VLSI Journal
Low-complexity adaptive decision-feedback equalization of MIMO channels
Signal Processing
Formal proof for a general architecture of hybrid prefix/carry-select adders
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Fast low-power 64-bit modular hybrid adder
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
CSD-RNS-based Single Constant Multipliers
Journal of Signal Processing Systems
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
Integration, the VLSI Journal
| Hi-index | 15.00 |
The carry-select or conditional-sum adders require carry-chain evaluations for each block for both the values of block-carry-in, 0 and 1. The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block with block-carry-in 0. This scheme is then applied to carry-select and parallel-prefix adders to derive a more area-efficient implementation for both the cases. The proposed carry-select scheme is assessed relative to carry-ripple, classical carry-select, and carry-skip adders. The analytic evaluation is done with respect to the gate-count model for area and gate-delay units for time.