Computer number systems and arithmetic
Computer number systems and arithmetic
The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Digital Computer Arithmetic
Introduction to VLSI Systems
Area-Time Optimal Adder Design
IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on computer arithmetic
Designing Optimum One-Level Carry-Skip Adders
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems
IEEE Transactions on Computers
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
IEEE Transactions on Computers
Performance evaluation of Manchester carry chain adder for VLSI designer library
SMO'05 Proceedings of the 5th WSEAS international conference on Simulation, modelling and optimization
A VLSI architecture for anti-aliasing
EGGH'89 Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware
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In this paper, we present a way to obtain efficient carry-skip adders, built with blocks of different sizes in VLSI technologies. We give some results about two-level carry-skip adders. We reduce our optimization problem to a geometrical problem, solved by means of an algorithm easily implemented on a microcomputer. Then we present an example of the realization of such an adder.