The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on computer arithmetic
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
A Fast Binary Adder with Conditional Carry Generation
IEEE Transactions on Computers
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
IEEE Transactions on Computers
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
Delay efficient 32-bit carry-skip adder
VLSI Design
| Hi-index | 14.99 |
The author shows how to design one-level carry-skip adders that attain very high speeds. One-level carry-skip adders are very fast adders that are hardly more complex than the much-slower ripple adders. The design procedure allows the use of realistic component delays obtained by simulation and is technology-independent. An example of a 64-b, 1 mu m CMOS adder is given. This adder achieves an add time of 6.23 ns, measured by SPICE simulation with realistic loads. This delay figure excludes sum buffering delays, which depend on the particular application of the adder. The combination of high-speed and simplicity makes one-level carry-skip adders attractive for applications in highly parallel systems.