Digital CMOS circuit design
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on computer arithmetic
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
Designing Optimum One-Level Carry-Skip Adders
IEEE Transactions on Computers
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
IEEE Transactions on Computers
A Fast Binary Adder with Conditional Carry Generation
IEEE Transactions on Computers
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
IEEE Transactions on Computers
A fast hybrid carry-lookahead/carry-select adder design
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
IEEE Transactions on Computers
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Robust high-performance low-power carry select adder
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A new redundant binary booth encoding for fast 2n-bit multiplier design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Formal proof for a general architecture of hybrid prefix/carry-select adders
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Fast low-power 64-bit modular hybrid adder
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The author presents a very fast adder for double-precision mantissas, which is an improvement on T. Lynch and E. E. Swartzlandes, Jr.'s spanning tree carry lookahead adder or redundant cell adder which was implemented using the Am29050 microprocessor. The adder presented is faster than theirs mainly because Manchester carry chains of various lengths are used instead of chains all of the same length.