High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
Fast multiplication: algorithms and implementation
Fast multiplication: algorithms and implementation
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IEEE Transactions on Computers
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IEEE Transactions on Computers
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers
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IEEE Transactions on Circuits and Systems for Video Technology
Flexible design of a modular simultaneous exponentiation core for embedded platforms
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
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The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired. However, its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary (NB) to RB number conversion. This paper proposes a new RB Booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent Booth encoded digits to directly form an RB partial product to avoid the hard multiple of high-radix Booth encoding without incurring any correction vector. The proposed method leads to lower encoding and decoding complexity than the recently proposed RB Booth encoder. Synthesis results using Artisan TSMC 0.18-µm standard-cell library show that the RB multipliers designed with our proposed Booth encoding algorithm exhibit on average 14% higher speed and 17% less energy-delay product than the existing multiplication algorithms for a gamut of power-of-two word lengths from 8 to 64 b.