Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
Digital Computer Arithmetic
Designing Optimum One-Level Carry-Skip Adders
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
Testability of Convergent Tree Circuits
IEEE Transactions on Computers
A Fast Binary Adder with Conditional Carry Generation
IEEE Transactions on Computers
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
IEEE Transactions on Computers
A fast hybrid carry-lookahead/carry-select adder design
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
On the properties of the input pattern fault model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
IEEE Transactions on Computers
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
Statistical Carry Lookahead Adders
IEEE Transactions on Computers
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
The input pattern fault model and its application
EDTC '97 Proceedings of the 1997 European conference on Design and Test
VLSI implementation of variable resolution image compression
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
An Effective BIST Scheme for Arithmetic Logic Un i t s
ITC '97 Proceedings of the 1997 IEEE International Test Conference
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
New algorithms for carry propagation
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Robust high-performance low-power carry select adder
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A new redundant binary booth encoding for fast 2n-bit multiplier design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Constructive threshold logic addition: a synopsis of the last decade
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
Speculative carry generation with prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal proof for a general architecture of hybrid prefix/carry-select adders
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Fast low-power 64-bit modular hybrid adder
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Mathematical and Computer Modelling: An International Journal
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout.