Dynamic CMOS circuit techniques for delay and power reduction in parallel adders

Authors:
H. Lindkvist;P. Andersson
Affiliations:
-;-
Venue:
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Year:
1995

Citing 12
Cited 0

Variants of an Improved Carry Look-Ahead Adder

IEEE Transactions on Computers
Area-Time Optimal Adder Design

IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip

IEEE Transactions on Computers
A Spanning Tree Carry Lookahead Adder

IEEE Transactions on Computers - Special issue on computer arithmetic
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder

IEEE Transactions on Computers
Parallel Prefix Computation

Journal of the ACM (JACM)
Introduction to VLSI Systems

Introduction to VLSI Systems
High-Speed Addition in CMOS

IEEE Transactions on Computers
Techniques for Fast CMOS-based Conditional Sum Adders

ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
New bounds for parallel prefix circuits

STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A Regular Layout for Parallel Adders

IEEE Transactions on Computers
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

The successful design of high-speed parallel adders depend mainly on fast calculation of carry signals. A technique based on combining Manchester-Carry chains (MCC) with Clock-and-Data pre-charged dynamic logic blocks (CDPD) is suggested and analysed. This technique, as well as pure MCC and CDPD techniques, was incorporated into the design of carry calculation trees. Simulations indicate that 11-25% decrease of delay at the same time as a 19-29% reduction of power consumption is made possible by combining MCCs with CDPD gates instead of using trees consisting solely of either MCCs of CDPD gates.