Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
Computing signal delay in general RC networks by tree/link partitioning
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Digital System Implementation
Introduction to VLSI Systems
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
IEEE Transactions on Computers - Special issue on computer arithmetic
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
Designing Optimum One-Level Carry-Skip Adders
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
IEEE Transactions on Computers
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
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Two different CMOS implementations of the Manchester carry-skip adder are analyzed using the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, the authors develop efficient polynomial algorithms to determine near-optimal (in latency) as well as optimal block sizes for the one-level manchester adder with variable carry-skip. An analysis shows that the carry-skip delay in a Manchester adder block is linearly proportional to the block size. The approach provides a general paradigm for analysis and design, applicable to different models of ripple-propagation and carry skip.