Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
Delay estimation for CMOS functional cells
EURO-DAC '91 Proceedings of the conference on European design automation
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Most RC simulators only handle tree networks, not arbitrary networks. We present an algorithm for computing signal delays in general RC networks using the RC-tree computation as the primary operation. We partition a given network into a spanning tree and link branches. Then we compute the signal delay of the spanning tree, and update the signal delay as we incrementally add the links back to reconstruct the original network. If m is the number of link branches, this algorithm requires m(m⊕1)/2 updates and m⊕1 tree delay evaluations. All the tree delay evaluations involve computing signal delays with the same resistive spanning tree, but with different values for the capacitors.