Delay estimation for CMOS functional cells

Authors:
Jan Madsen
Affiliations:
Technical University of Denmark, Lyngby, Denmark
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

Citing 2
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Abstract

This paper presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.