Relaxation techniques for the simulation of VLSI circuits
Relaxation techniques for the simulation of VLSI circuits
Delay optimization of combinational static CMOS logic
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An accuration delay modeling technique for switch-level timing verification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Graph Algorithms
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Delay estimation for CMOS functional cells
EURO-DAC '91 Proceedings of the conference on European design automation
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This paper presents two algorithms for performing worst-case delay estimation using transistor-level timing simulation techniques. The first algorithm, Dynamic Path Selection (DPS), determines in linear time the slowest paths in series-parallel transistor groups; the exponential complexity remains for transistor groups with bridges. The second algorithm, Delay Subnetwork Enumeration (DSE), complements the DPS method by taking into account logic dependencies within transistor groups. The two methods are combined in the static timing analyzer TAMIA, to provide accurate worst-case delay estimation of digital CMOS circuits.