Computing signal delay in general RC networks by tree/link partitioning
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Process-variation-tolerant clock skew minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Matrix computations (3rd ed.)
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast simulation of VLSI interconnects
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Steiner network construction for timing critical nets
Proceedings of the 43rd annual Design Automation Conference
Discrete buffer and wire sizing for link-based non-tree clock networks
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Utilizing redundancy for timing critical interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Discrete buffer and wire sizing for link-based non-tree clock networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Crosslink insertion for variation-driven clock network construction
Proceedings of the great lakes symposium on VLSI
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We present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. Monte Carlo simulations show that the robustness of the final clock network can be significantly improved with a small increase in wire length.