Process-variation-tolerant clock skew minimization

Authors:
Shen Lin;C. K. Wong
Affiliations:
IBM T.J. Watson Research Center, Yorktown Heights, NY;IBM T.J. Watson Research Center, Yorktown Heights, NY
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

Citing 3
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Abstract

In this paper, we propose a novel hierarchical multiple-merge zero skew clock routing algorithm. The routing results produced by our approach will have zero skew in the nominal case and minimal skew increase in the presence of worst process variations. In order to construct such a clock routing, we formulate the linear placement with maximum spread problem and provide an O(nmin{n,P}lognlogP) algorithm for optimally solving this problem, where n is the number of cells to be placed and P is the maximum spread. Experimental results show that our algorithm can indeed reduce the skew in various manufacturing variations effectively.