A graph theoretic technique to speed up floorplan area optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Skew sensitivity minimization of buffered clock tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Process-variation-tolerant clock skew minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Planar clock routing for high performance chip and package co-design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
More practical bounded-skew clock routing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Planar-DME: a single-layer zero-skew clock tree router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-processing of clock trees via wiresizing and buffering for robust design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
The associative-skew clock routing problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Practical approximation algorithms for zero- and bounded-skew trees
SODA '01 Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Clock network sizing via sequential linear programming with time-domain analysis
Proceedings of the 2004 international symposium on Physical design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Register placement for low power clock network
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Process variation robust clock tree routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Associative skew clock routing for difficult instances
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Legitimate Skew Clock Routing with Buffer Insertion
Journal of VLSI Signal Processing Systems
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
System level clock tree synthesis for power optimization
Proceedings of the conference on Design, automation and test in Europe
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
Contango: integrated optimization of SoC clock networks
Proceedings of the Conference on Design, Automation and Test in Europe
Buffered clock tree sizing for skew minimization under power and thermal budgets
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2011 international symposium on Physical design
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
Clock tree synthesis with methodology of re-use in 3D IC
Proceedings of the 49th Annual Design Automation Conference
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration, the VLSI Journal
Clock mesh synthesis with gated local trees and activity driven register clustering
Proceedings of the International Conference on Computer-Aided Design
Low-power anti-aging zero skew clock gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sparse-rotary oscillator array (SROA) design for power and skew reduction
Proceedings of the Conference on Design, Automation and Test in Europe
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Agglomerative-based flip-flop merging with signal wirelength optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
We study the minimum-cost bounded-skew routing tree problem under the pathlength (linear) and Elmore delay models. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. Our bounded-skew routing algorithm, called the BST/DME algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a merging region. For a prescribed topology, BST/DME constructs a bounded-skew tree (BST) in two phases: (i) a bottom-up phase to construct a binary tree of merging regions which represent the loci of possible embedding points of the internal nodes, and (ii) a top-down phase to determine the exact locations of the internal nodes. We present two approaches to construct the merging regions: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to the boundaries of merging regions, and (ii) the Interior Merging and Embedding (IME) algorithm which employs a sampling strategy and a dynamic programming-based selection technique to consider merging points that are interior to, as well as on the boundary of, the merging regions. When the topology is not prescribed, we propose a new Greedy-BST/DME algorithm which combines the merging region computation with topology generation. The Greedy-BST/DME algorithm very closely matches the best known heuristics for the zero-skew case and for the unbounded-skew case (i.e., the Steiner minimal tree problem). Experimental results show that our BST algorithms can produce a set of routing solutions with smooth skew and wire length tradeoffs.