Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A sliding window scheme for accurate clock mesh analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2009 international symposium on Physical design
Minimizing clock latency range in robust clock tree synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A dual-MST approach for clock network synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
VLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
Novel binary linear programming for high performance clock mesh synthesis
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing analysis including clock skew
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This mini-tutorial covers recent research on clock-network tuning. It starts with SPICE-accurate optimizations used in winning entries at the ISPD 2009 and 2010 clock-network synthesis contests. After comparing clock trees to meshes, it outlines a recent redundant clock-network topology that retains most advantages of clock trees, but improves robustness to PVT variations. It also shows how to incorporate clock-network synthesis into global placement to reduce dynamic power and insertion delay.