A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Fast algorithms for slew constrained minimum cost buffering
Proceedings of the 43rd annual Design Automation Conference
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion with adaptive blockage avoidance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
A new clock network synthesizer for modern VLSI designs
Integration, the VLSI Journal
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Given the extensive study of clock skew minimization, in the ISPD 2009 Clock Network Synthesis (CNS) Contest, clock latency range (CLR) was initially minimized across multiple supply voltages under capacitance and slew constraints. CLR approximates the summation of the clock skew and the maximum source-to-sink delay variation for multiple supply voltages. This work develops an efficient three-stage clock tree synthesis flow for CLR minimization. Firstly, a balanced clock tree with small skew is generated. Secondly, buffer insertion and wire sizing minimizes delay variation without violating the slew constraint. Finally, skew is minimized by inserting snaking wires. Experimental results reveal that the proposed flow can complete all ISPD'09 benchmark circuits and yield less CLR than the top three winners of ISPD'09 CNS contest by 59%, 52.7% and 35.4% respectively. Besides, the proposed flow can also run 5.52, 1.86, and 7.54 times faster than the top three winners of ISPD'09 CNS contest respectively.