Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ICCAD '00 Proceedings of the 2000 international conference on Computer-aided design
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
Robust chip-level clock tree synthesis for SOC designs
Proceedings of the 45th annual Design Automation Conference
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Minimizing clock latency range in robust clock tree synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A dual-MST approach for clock network synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing clock skew variability via crosslinks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total performance of the chip. Both the clock skew and the PVT (process, voltage and temperature) variations contribute a lot to the behavior of the digital circuits. Previous works mainly focused on skew and wirelength minimization. However, it may lead to negative influence on the variation factors. In this paper, a novel clock tree synthesizer is proposed for performance improvement. Several algorithms are introduced to tackle the issues accordingly. A dual-MST geometric approach of perfect matching is developed for symmetric clock tree construction. In addition, a special technique of buffer sizing is also introduced. These two techniques can help balancing the tree structure in order to reduce the variation effect. An iterative buffer insertion technique and the dual-MZ blockage handling technique are also presented. They are developed for proper distribution of buffers and connection of wires, so the dynamic power consumption can be reduced. Additionally, slew table construction and internal nodes relocation are involved to satisfy the slew rate constraint and further reduce the clock skew. Experimental results show that the performance of our synthesizer is better than those of the previous works.