Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A buffer distribution algorithm for high-speed clock routing
DAC '93 Proceedings of the 30th international Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ICCAD '00 Proceedings of the 2000 international conference on Computer-aided design
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
Robust chip-level clock tree synthesis for SOC designs
Proceedings of the 45th annual Design Automation Conference
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Reducing clock skew variability via crosslinks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock network synthesis with concurrent gate insertion
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
A new clock network synthesizer for modern VLSI designs
Integration, the VLSI Journal
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Voltage and Temperature) variations contribute a lot to its behavior. Previous works mainly focused on skew and wirelength minimization. It may lead to negative influence towards these process variation factors. In this paper, a novel clock network synthesizer is proposed and several algorithms are introduced for performance improvement. A dual-MST (DMST) geometric matching approach is proposed for topology construction. It can help balancing the tree structure to reduce the variation effect. A recursive buffer insertion technique and a blockage handling method are also presented, and they are developed for proper distribution of buffers and saving of capacitance. Experimental results show that our matching approach is better than the traditional methods, and in particular our synthesizer has better performance compared to the results of the winner in the ISPD 2009 contest.