Buffer insertion and sizing under process variations for low power clock distribution

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Useful-skew clock routing with gate sizing for low power design

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Constructing lower and upper bounded delay routing trees using linear programming

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Jitter-tolerant clock routing in two-phase synchronous systems

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Power Optimization in VLSI Layout: A Survey

Journal of VLSI Signal Processing Systems

Clock Skew Optimization for Peak Current Reduction

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Useful-Skew Clock Routing with Gate Sizing for Low Power Design

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Practical Bounded-Skew Clock Routing

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

A min-cost flow based min-cost rectilinear Steiner distance-preserving tree construction

Proceedings of the 1997 international symposium on Physical design

Bounded-skew clock and Steiner routing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Buffer insertion for clock delay and skew minimization

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Process variation aware clock tree routing

Proceedings of the 2003 international symposium on Physical design

Power-aware clock tree planning

Proceedings of the 2004 international symposium on Physical design

Buffer sizing for clock power minimization subject to general skew constraints

Proceedings of the 41st annual Design Automation Conference

Clock skew bounds estimation under power supply and process variations

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Practical techniques to reduce skew and its variations in buffered clock networks

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Low power clock buffer planning methodology in F-D placement for large scale circuit design

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Power efficient tree-based crosslinks for skew reduction

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Discrete buffer and wire sizing for link-based non-tree clock networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A new clock network synthesizer for modern VLSI designs

Integration, the VLSI Journal

Revisiting automated physical synthesis of high-performance clock networks

ACM Transactions on Design Automation of Electronic Systems (TODAES)

In-placement clock-tree aware multi-bit flip-flop generation for power optimization

Proceedings of the International Conference on Computer-Aided Design