Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire Sizing for Non-Tree Topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven variation-aware nonuniform clock mesh synthesis
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks
Integration, the VLSI Journal
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Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered.