Computational geometry: an introduction
Computational geometry: an introduction
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Timing Optimization Through Clock Skew Scheduling
Timing Optimization Through Clock Skew Scheduling
Power efficient tree-based crosslinks for skew reduction
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Reducing clock skew variability via crosslinks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2011 international symposium on Physical design
Clock mesh synthesis with gated local trees and activity driven register clustering
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-corner multi-voltage domain clock mesh design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks
Integration, the VLSI Journal
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Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37% average reduction in metal consumption and 39% average reduction in power dissipation, while insignificantly increasing the maximum skew.