Sizing of clock distribution networks for high performance CPU chips

A Clock Methodology for High-Performance Microprocessors

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Optimal wire and transistor sizing for circuits with non-tree topology

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

A pseudo-hierarchical methodology for high performance microprocessor design

Proceedings of the 1997 international symposium on Physical design

Hybrid structured clock network construction

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

On-Chip Clock Faults' Detector

Journal of Electronic Testing: Theory and Applications

Concurrent Checking of Clock Signal Correctness

IEEE Design & Test

Process variation aware clock tree routing

Proceedings of the 2003 international symposium on Physical design

On-Line Testing Scheme for Clock's Faults

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing

IEEE Transactions on Computers

Clock network sizing via sequential linear programming with time-domain analysis

Proceedings of the 2004 international symposium on Physical design

Reducing clock skew variability via cross links

Proceedings of the 41st annual Design Automation Conference

A multiple level network approach for clock skew minimization with process variations

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Improved algorithms for link-based non-tree clock networks for skew variability reduction

Proceedings of the 2005 international symposium on Physical design

Analysis of buffered hybrid structured clock networks

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

A multi-level transmission line network approach for multi-giga hertz clock distribution

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

A sliding window scheme for accurate clock mesh analysis

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

An efficent clustering algorithm for low power clock tree synthesis

Proceedings of the 2007 international symposium on Physical design

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

IEEE Transactions on Computers

MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors

Proceedings of the 2009 international symposium on Physical design

Low-power rotary clock array design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Accurate clock mesh sizing via sequential quadraticprogramming

Proceedings of the 19th international symposium on Physical design

Timing-driven variation-aware nonuniform clock mesh synthesis

Proceedings of the 20th symposium on Great lakes symposium on VLSI

Non-uniform clock mesh optimization with linear programming buffer insertion

Proceedings of the 47th Design Automation Conference

Clock skew optimization considering complicated power modes

Proceedings of the Conference on Design, Automation and Test in Europe

Discrete buffer and wire sizing for link-based non-tree clock networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Meshworks: a comprehensive framework for optimized clock mesh network synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Distributed Resonant clOCK grid Synthesis (ROCKS)

Proceedings of the 48th Design Automation Conference

Novel binary linear programming for high performance clock mesh synthesis

Proceedings of the International Conference on Computer-Aided Design

High-performance clock mesh optimization

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world

Revisiting automated physical synthesis of high-performance clock networks

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks

Integration, the VLSI Journal