A pseudo-hierarchical methodology for high performance microprocessor design

• Authors:

• A. Bertolet;K. Carpenter;K. Carrig;A. Chu;A. Dean;F. Ferraiolo;S. Kenyon;D. Phan;J. Petrovick;G. Rodgers;D. Willmott;T. Bairley;T. Decker;V. Girardi;Y. Lapid;M. Murphy;P. A. Scott;R. Weiss

• Affiliations:

• IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;IBM Corporation, Essex Junction, Vermont;Cadence Design Systems, San Jose, California;Cadence Design Systems, San Jose, California;Cadence Design Systems, San Jose, California;Cadence Design Systems, San Jose, California;Cadence Design Systems, San Jose, California;Cadence Design Systems, San Jose, California;Cadence Design Systems, San Jose, California

• Venue:
• Proceedings of the 1997 international symposium on Physical design
• Year:
• 1997