Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
A pseudo-hierarchical methodology for high performance microprocessor design
Proceedings of the 1997 international symposium on Physical design
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SOI digital CMOS VLSI—a design perspective
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
SOI circuit design concepts
A semi-custom design flow in high-performance microprocessor design
Proceedings of the 38th annual Design Automation Conference
Technical visualizations in VLSI design: visualization
Proceedings of the 38th annual Design Automation Conference
In the Driver's Seat of BooleDozer
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
POWER4 system microarchitecture
IBM Journal of Research and Development
Infrastructure requirements for a large-scale, multi-site VLSI development project
IBM Journal of Research and Development
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Design methodology for semi custom processor cores
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
Timing optimization by replacing flip-flops to latches
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IBM Journal of Research and Development - Electrochemical technology in microelectronics
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IBM Journal of Research and Development - POWER5 and packaging
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
IntSim: A CAD tool for optimization of multilevel interconnect networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IBM POWER6 microprocessor physical design and design methodology
IBM Journal of Research and Development
Power-constrained high-frequency circuits for the IBM POWER6 microprocessor
IBM Journal of Research and Development
Conditional data mapping flip-flops for low-power and high-performance systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
POWER4 system microarchitecture
IBM Journal of Research and Development
Register placement for high-performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
Power management and its impact on power supply noise
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.