Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Performance modeling for early analysis of multi-core systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Three-dimensional silicon integration
IBM Journal of Research and Development
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Robust power gating reactivation by dynamic wakeup sequence throttling
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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As device sizes continue to shrink and circuit complexity continues to grow, power has become the limiting factor in today’s processor designs. This paper describes a hierarchical scalable power supply noise analysis methodology to simulate the switching events that arise from the ubiquitous use of clock gating, power gating, frequency scaling, and other power management techniques. By accurately extracting and modeling the electrical characteristics of both the package and chip design, our multi-core multi-voltage-domain transient noise analysis ensures the power and signal integrity of our design under different workloads and operating frequencies. A series of case studies will be presented to illustrate the effect of power management operations on transient noise and the design of a power management control unit to contain voltage droop.