Design methodology for the IBM POWER7 microprocessor

  • Authors:

  • Joshua Friedrich;Ruchir Puri;Uwe Brandt;Markus Buehler;Jack DiLullo;Jeremy Hopkins;Mozammel Hossain;Michael Kazda;Joachim Keinert;Zahi M. Kurzum;Douglass Lamb;Alice Lee;Frank Musante;Jens Noack;Peter J. Osler;Stephen Posluszny;Haifeng Qian;Shyam Ramji;Vasant Rao;Lakshmi N. Reddy;Haoxing Ren;Thomas Rosser;Benjamin R. Russell;Cliff Sze;Gustavo Téllez

  • Affiliations:

  • IBM Systems and Technology Group, Austin, TX;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Austin, TX;IBM Systems and Technology Group, Austin, TX;IBM Systems and Technology Group, Austin, TX;IBM Systems and Technology Group, East Fishkill, NY;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Research Triangle Park, NC;IBM Systems and Technology Group, Lexington, MA;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Essex Junction, VT;IBM Systems and Technology Group, Austin, TX;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Yorktown Heights, NY;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, NY;IBM Systems and Technology Group, Austin, TX;IBM Systems and Technology Group, Waltham, MA;IBM Research Division, Austin Research Laboratory, Austin, TX;IBM Systems and Technology Group, Essex Junction, VT

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2011

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Abstract

The IBM POWER7® microprocessor, which is the next-generation IBM POWER® processor, leverages IBM's 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex 567-mm2 die, the IBM design team made significant innovations in chip design methodology. This paper describes the most critical methodology innovations specific to POWER7 design, which were in modularity, timing closure, and design efficiency.